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Electrical Characteristics (T J = 25°C, V CC =V BS =15V Unless Otherwise Specified)
Inverter Part (Each FRFET Unless Otherwise Specified)
Symbol
Parameter
Conditions
Min Typ Max Units
BV DSS
Δ BV DSS /
Δ T J
I DSS
R DS(on)
V SD
t ON
t OFF
t rr
E ON
E OFF
Drain-Source Breakdown
Voltage
Breakdown Voltage Tem-
perature Coefficient
Zero Gate Voltage
Drain Current
Static Drain-Source
On-Resistance
Drain-Source Diode
Forward Voltage
Switching Times
V IN = 0V, I D = 250 μ A (Note 2)
I D = 250 μ A, Referenced to 25°C
V IN = 0V, V DS = 500V
V CC = V BS = 15V, V IN = 5V, I D = 1.2A
V CC = V BS = 15V, V IN = 0V, I D = -1.2A
V PN = 300V, V CC = V BS = 15V, I D = 1.2A
V IN = 0V ? 5V
Inductive load L=3mH
High- and low-side FRFET switching
(Note 3)
500
-
-
-
-
-
-
-
-
-
-
0.53
-
1.0
-
600
500
100
60
10
-
-
250
1.4
1.2
-
-
-
-
-
V
V
μ A
Ω
V
ns
ns
ns
μ J
μ J
RBSOA
Reverse-bias Safe Oper-
ating Area
V PN = 400V, V CC = V BS = 15V, I D = I DP, V DS =BV DSS ,
T J = 150°C
High- and low-side FRFET switching (Note 4)
Full Square
Control Part (Each HVIC Unless Otherwise Specified)
Symbol
Parameter
Conditions
Min Typ Max Units
I QCC
I QBS
Quiescent V CC Current
Quiescent V BS Current
V CC =15V, V IN =0V
V BS =15V, V IN =0V
Applied between V CC and COM
Applied between V B(U) -U,
V B(V) -V, V B(W) -W
-
-
-
-
160
100
μ A
μ A
UV CCD
UV CCR
UV BSD
UV BSR
Low-side Undervoltage
Protection (Figure 6)
High-side Undervoltage
Protection (Figure 7)
V CC Undervoltage Protection Detection Level
V CC Undervoltage Protection Reset Level
V BS Undervoltage Protection Detection Level
V BS Undervoltage Protection Reset Level
7.4
8.0
7.4
8.0
8.0
8.9
8.0
8.9
9.4
9.8
9.4
9.8
V
V
V
V
V IH
V IL
I IH
I IL
ON Threshold Voltage
OFF Threshold Voltage
Input Bias Current
Logic High Level
Logic Low Level
V IN = 5V
V IN = 0V
Applied between IN and COM
Applied between IN and COM
3.0
-
-
-
-
-
10
-
-
0.8
20
2
V
V
μ A
μ A
Note:
1. For the measurement point of case temperature T C , please refer to Figure 3 in page 4.
2. BV DSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM ? . V PN should be sufficiently less than this value considering the
effect of the stray inductance so that V DS should not exceed BV DSS in any case.
3. t ON and t OFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5.
4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 5 for the RBSOA test cir-
cuit that is same as the switching test circuit.
Package Marking & Ordering Information
Device Marking
FSB50550U
Device
FSB50550U
Package
SPM23-AD
Reel Size
_
Packing Type
_
Quantity
15
FSB50550U Rev. A
3
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